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low power stereo audio adc revision 6 .0 november 2016 1 ES8288 general description features ES8288 is a high performance, low power and low cost audio adc. it consists of 2 - ch adc, microphone amplifier and auto level control. the device uses advanced multi - bit delta - sigma modulation technique to convert data betw een digital and analog. the multi - bit delta - sigma modulator s make the device with low sensitivity to clock jitter and low out of band noise . adc ? 24- bit, 8 khz to 96 khz sampling frequency ? 95 db dynamic range, 95 db signal to noise ratio, - 85 db thd+n ? s tereo or mono microphone interface with microphone amplifier ? auto level control and noise gate ? 2 - to - 1 analog input selection low power ? 1.8v to 3.3v operation ? 9 mw recording system ? i 2 c or spi uc interface ? 256fs, 384fs, usb 12 mhz or 24 mhz ? master or slave s erial port ? i 2 s, left justified, dsp/pcm mode applications ordering information ? portable audio recording ES8288 - 40 c ~ +85 c qfn - 28
everest semiconductor ES8288 revision 6 .0 november 2016 2 1 block diagram ..................................................................................... 3 2 28- pin qfn and pin desc riptions .................................................... 4 3 typical application circuit ............................................................ 6 4 clock modes and samp ling frequenci es .................................. 6 5 micro - controller configura tion interface ......................... 8 5.1 spi ...................................................................................................... 8 5.2 2 - wire .................................................................................................. 9 6 configuration regist er definition .......................................... 10 6.1 chip control and power management .............................................. 11 6.1.1 register 0 ? chip control 1, default 0000 0110 .......................... 11 6.1.2 register 1 ? chip control 2, default 0001 1100 .......................... 11 6.1.3 register 2 ? chip power management, default 1100 0011 ......... 11 6.1.4 register 3 ? adc power management, default 1111 1100 ......... 12 6.1.5 register 5 ? chip low power 1, default 0000 0000 .................... 12 6.1.6 register 6 ? chip low power 2, default 0000 0000 .................... 12 6.1.7 register 7 ? analog voltage management, default 0111 1100 .... 12 6.1.8 register 8 ? master mode control, default 1000 0000 ............... 13 6.2 ad c control ...................................................................................... 13 6.2.1 register 9 ? adc control 1, default 0000 0000 .......................... 13 6.2.2 register 10 ? adc control 2, default 0000 0000 ........................ 13 6.2.3 register 11 ? adc control 3, default 0000 0110 ........................ 14 6.2.4 register 12 ? adc control 4, default 0000 0000 ........................ 14 6.2.5 register 13 ? adc control 5, default 0000 0110 ........................ 14 6.2.6 register 14 ? adc control 6, default 0011 0000 ........................ 15 6.2.7 register 15 ? adc control 7, default 0011 0000 ........................ 15 6.2.8 register 16 ? adc control 8, default 1100 0000 ........................ 16 6.2.9 register 17 ? adc control 9, default 1100 0000 ........................ 16 6.2.10 register 18 ? adc control 10, default 0011 1000 ...................... 16 6. 2.11 register 19 ? adc control 11, default 1011 0000 ...................... 17 6.2.12 register 20 ? adc control 12, default 0011 0010 ...................... 17 6.2.13 registe r 21 ? adc control 13, default 0000 0110 ...................... 18 6.2.14 register 22 ? adc control 14, default 0000 0000 ...................... 18 6.2.15 register 43 ? adc c ontrol 15, default 0011 1000 ...................... 18 7 digital audio interface .............................................................................. 19 8 electrical character istics ........................................................ 20 8.1 absolute maximum ratings ............................................................... 20 8.2 recommended operating conditions ............................................... 20 8.3 adc analog and filter c haracteristics and specifications ................ 20 8.4 power consumption characteristics ................................................. 21 8.5 serial audio port switching specifications ........................................ 21 8.6 serial control port switching specifications ...................................... 22 9 package information ...................................................................... 24 10 corpoaration information ....................................................... 25
everest semiconductor ES8288 revision 6 .0 november 2016 3 1 block diagram mic amp adc mux alc micl+micr mic amp a dc mux alc micl+micr dvdd pvdd dgnd avdd agnd avdd agnd vref vmid mclk clock manager uc interface ce cclk cdata serial audio data asdout lrck dsdin sclk mux rin1 rin2 lin1- rin1 lin2- rin2 mux lin1 lin2 lin1- rin1 lin2- rin2
everest semiconductor ES8288 revision 6 .0 november 2016 4 2 28- pin qfn and pin desc riptions cclk c data ce nc lin1 rin1 lin2 rin2 vmid adcvref agnd avdd nc nc asdout nc nc nc nc agnd nc mclk dvdd pvdd dgnd sclk dgnd lrck 8 9 10 11 12 13 14 21 20 19 18 17 16 15 28 27 26 25 24 23 22 1 2 3 4 5 6 7
everest semiconductor ES8288 revision 6 .0 november 2016 5 pin name i/o description 1 mclk i master clock 2 dvdd supply digital core supply 3 p vdd supply digital io supply 4 dgnd supply digital ground (return path for both dvdd and p vdd) 5 s clk i/o audio data bit clock 6 dgn d i connect to ground 7 lrck i adc audio data left and right clock 8 asdo ut o adc audio data 9 nc nc no connect 10 nc nc no connect 11 nc nc no connect 12 nc nc no connect 13 agnd supply analog ground 14 nc nc no connect 1 5 nc nc no connect 1 6 nc nc no connect 1 7 avdd supply analog supply 1 8 agnd supply analog ground 19 adc vref o d ecoupling capacitor 2 0 vmid o d ecoupling capacitor 2 1 rin2 i right channel input 2 2 2 lin2 i left channel input 2 2 3 rin1 i right channel input 1 2 4 lin1 i left channel input 1 2 5 nc nc no connect 26 c e i control select or d evice address selection 27 cdata i/o control data input or output 28 cclk i control clock input
everest semiconductor ES8288 revision 6 .0 november 2016 6 3 typical application circuit av dd i 2s_mclk i 2s_sclk i 2s_lrck i 2s_a sdo ut gn d 0.1uf gn d i 2c/spi dat a i 2c/spi clk 4.7uf 4.7uf mi c 1k 2k 0.1uf + 10uf gn d av dd gn d 2k 4.7uf 0.1uf 4.7uf 0.01uf 0.01uf 10 4.7uf 0.1uf gn d i 2c ad0 / sp i ce bead 4.7uf 0.1uf 0.1uf gn d av dd gn d av dd vi n 1 gnd 2 vo ut 3 l m11 17 - 3. 3v gn d vcc av dd + 10uf + 10uf 0.1uf 0.1uf one ldo is recommended to provide power supply to ES8288 gn d gn d mc lk 1 dv dd 2 dg nd 4 pv dd 3 s clk 5 gn d 6 lr ck 7 asd out 8 nc 9 nc 16 nc 15 nc 14 agn d 13 nc 12 nc 11 av dd 17 ag nd 18 vmid 20 ri n2 21 lin2 22 rin1 23 lin1 24 nc 25 ce 26 cda ta 27 cclk 28 ad cvref 19 nc 10 gnd 29 ES8288 4.7k 4.7k av dd 4.7uf 4.7uf li n1 ri n1 gn d pin9,pin10,pin11,pin12,pin14 and pin15 must be float, don't connect these pins to ground. 4 clock modes and samp ling frequencies according to the input serial audio data sampling frequency, the device can work in two speed modes: single speed or double speed. the ranges of the sampling frequency in these two modes are listed in table 1. the device can work either in master clock mode or slave clock mode. in slave mode, lrck and sclk are supplied externally. lrck and sclk must be synchronously derived from the system clock with specific rates. the device can auto detect mclk/lrck ratio according to table 1. the device only support s the mclk/lrck ratios li sted in table 1. the lrck/sclk ratio is normally 64. table 1 slave mode sampling frequencies and mclk /lrck ratio speed mode sampling frequency mclk /lrck ratio single speed 8khz ? 50khz 256, 384, 512, 768, 1024 double speed 50khz ? 100khz 128, 192, 256, 384, 512 in master mode, lrck and sclk are derived internally from mclk. the available mclk/lrck ratios and sclk/lrck ratios are listed in table 2.
everest semiconductor ES8288 revision 6 .0 november 2016 7 table 2 master mode sampling frequencies and mclk /lrck ratio mclk clkdiv2=0 mclk clkdiv2=1 adc sample ra te (alrck) adcfsratio [4:0] sclk ratio 12.288 mhz 24.576mhz 8 khz (mclk/1536) 01010 mclk/6 8 khz (mclk/1536) 01010 mclk/4 12 khz (mclk/1024) 00111 mclk/4 16 khz (mclk/768) 00110 mclk/6 24 khz (mclk/512) 00100 mclk/4 32 khz (mc lk/384) 00011 mclk/6 48 khz (mclk/256) 00010 mclk/4 48 khz (mclk/256) 00010 mclk/4 96 khz (mclk/128) 00000 mclk/2 11.2896 mhz 22.5792mhz 8.0182 khz (mclk/1408) 01001 mclk/4 8.0182 khz (mclk/1408) 01001 mclk/4 11.025 khz (mclk/10 24) 00111 mclk/4 22.05 khz (mclk/512) 00100 mclk/4 44.1 khz (mclk/256) 00010 mclk/4 44.1 khz (mclk/256) 00010 mclk/4 88.2 khz (mclk/128) 00000 mclk/2 18.432 mhz 36.864mhz 8 khz (mclk/2304) 01100 mclk/6 8 khz (mclk/2304) 01100 mclk/6 12 khz (mclk/1536) 01010 mclk/6 16 khz (mclk/1152) 01000 mclk/6 24 khz (mclk/768) 00110 mclk/6 32 khz (mclk/576) 00101 mclk/6 48 khz (mclk/384) 00011 mclk/6 48 khz (mclk/384) 00011 mclk/6 96 khz (mclk/192) 00001 mc lk/3 16.9344 mhz 33.8688mhz 8.0182 khz (mclk/2112) 01011 mclk/6 8.0182 khz (mclk/2112) 01011 mclk/6 11.025 khz (mclk/1536) 01010 mclk/6 22.05 khz (mclk/768) 00110 mclk/6 44.1 khz (mclk/384) 00011 mclk/6 44.1 khz (mclk/384) 00011 mclk/6 88.2 khz (mclk/192) 00001 mclk/3 12 mhz 24mhz 8 khz (mclk/1500) 11011 mclk 8 khz (mclk/1500) 11011 mclk 8.0214 khz (mclk/1496) 11010 mclk 8.0214 khz (mclk/1496) 11010 mclk 11.0259 khz (mclk/1088) 11001 mclk 12 khz ( mclk/1000) 11000 mclk
everest semiconductor ES8288 revision 6 .0 november 2016 8 16 khz (mclk/750) 10111 mclk 22.0588 khz (mclk/544) 10110 mclk 24 khz (mclk/500) 10101 mclk 32 khz (mclk/375) 10100* mclk 44.118 khz (mclk/272) 10011 mclk 44.118 khz (mclk/272) 10011 mclk 48 khz (mcl k/250) 10010 mclk 48 khz (mclk/250) 10010 mclk 88.235 khz (mclk/136) 10001 mclk 96 khz (mclk/125) 10000 mclk 5 micro - controller configura tion interface the device supports standard spi and 2 - wire micro - controller configuration interface. e xternal micro - controller can completely configure the device through writing to internal configuration registers. please see section 8 for the details of configuration register definition. the identical device pins are used to configure either spi or 2 - wi re interface. in spi mode, pin ce, cclk and cdata function as spi_csn, spi_clk and spi_din. in 2 - wire mode, pin ce, cclk and cdata function as ad0 , scl and sda. to select spi mode, apply high to low transition signal to ce pin . otherwise the device will op erate in 2 - wire interface mode. 5.1 spi ES8288 has a spi (serial peripheral interface) compliant synchronous serial slave controller inside the chip . it provides the ability to allow the external master spi controller to access the internal registers, and thus control the operations of chip . all lines on the spi bus are unidirectional: the spi_clk is generated by the master controller and is primarily used to synchronize data transfer, the spi_din line carries data from the master to the slave ; spi_csn is gene rated by the master to select ES8288. the timing diagram of this interface is given in figure 1. the high to low transition at spi_csn pin indicates the spi interface selected. each write procedure contains 3 words, i.e. chip address plus r/w bit, interna l register address and internal register data. every word length is fixed at 8 bits. the input spi_din data are sampled at the rising edge of spi_clk clock. the msb bit in each word is transferred firstly. the transfer rate can be up to 10m bps.
everest semiconductor ES8288 revision 6 .0 november 2016 9 chip address 7 bits - 0010000 0 spi_din spi_clk spi_csn 1 r/ wb 5 6 7 8 9 14 15 16 17 22 23 ram 8 bits register data 8 bits 5.2 2 - wire 2 - wire interface is a bi - directional serial bus that uses a serial data line (sda) and a serial clock line (scl) for data transfer. the timing diagram for data transfer of this interface is given in figure 2. data are transmit ted synchronously to scl clock on the sda line on a byte - by - byte basis. each bit in a byte is sampled during scl high with msb bit being transmitted firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the sda low. the tra nsfer rate of this interface can be up to 100k bps. a master controller initiates the transmission by sending a ?start? signal, which is defined as a high - to - low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. the chip address must be 001000x,where x equals ad0 (pin ce) . the rw bit indicates the slave data transfer direction. once an acknowledge bit is received, the data transfer starts to proceed on a byte - by - by te basis in the direction specified by the rw bit. the master can terminate the communication by generating a ?stop? signal, which is defined as a low - to - high transition at sda while scl is high. in 2 - wire interface mode, the registers can be written and read. the formats of ?write? and ?read? instructions are shown in table 3 and table 4. please note that, to read data from a register, you must set r/w bit to 0 to access the register address and then set r/w to 1 to read data from the register. figure 1 spi configuration interface timing diagram ram = register address mapping figure 2 complete data transfer for 2 - wire interface
everest semiconductor ES8288 revision 6 .0 november 2016 10 table 3 w rite data to register in 2 - wire interface mode chip address r/w register address data to be written 001000 ad0 0 ack ram ack data table 4 read data from register in 2 - wire interface mode chip address r/w register address 001000 ad0 0 ack ram chip address r/w data to be read 001000 ad0 1 ack data 6 configuration regist er definition spi and 2 - wire configuration interface share the same registers because there is only one interface active at any time. there are total of 53 user programmable 8 - bit registers in this device. these registers control the operations of adc and dac. external master controller can access these registers by using the slave address specified in ram (register address map) register as shown in the t able 5. table 5 bit content of register address map b7 b6 b5 b4 b3 b2 b1 b0 reg. 00 scpreset lrcm seqen enref vmidsel reg. 01 tsden pdnoc lpvcmmod lpvrefbuf pdnana pdnibiasgen vrefrlo pdnvrefbuf reg. 02 adc_digpdn adc_stm_rst adcdll_pdn adcvref_ pdn reg. 03 pdnainl pdnainr pdnadcl pdnadcr pdnmicb pdnadcbiasgen flashlp int1lp reg. 05 oc[2] oc[3] reg. 06 lppga lpadcvrp reg. 07 vsel reg. 08 msc mclkdiv2 bclk_inv bclkdiv reg. 09 micampl micampr reg. 10 linsel rinsel reg. 11 ds tri oc[1:0] reg. 12 datsel adclrp adcwl adcformat reg. 13 adcfsmode adcfsratio reg. 14 adc_invl adc_invr adc_hpf_l adc_hpf_r reg. 15 adcramprate adcsoftramp adczerocrs adcler adcmute reg. 16 ladcvol reg. 17 radcvol reg. 1 8 alcsel maxgain mingain reg. 19 alclvl alchld reg. 20 alcdcy alcatk reg. 21 alcmode alczc time_out win_size
everest semiconductor ES8288 revision 6 .0 november 2016 11 reg. 22 ngth ngg ngat reg. 43 slrck lrck_sel a dc_dll_pwd 6.1 chip control and power management 6.1.1 register 0 ? chip control 1 , default 000 0 0110 bit name bit description scpreset 7 0 ? normal (default) 1 ? reset control port register to default lrcm 6 0 ? alrck disabled when both adc disabled; dlrck disabled when both dac disabled (default) 1 ? alrck and dlrck disabled when all adc and da c disabled s eqe n 3 0 ? internal power up/down sequence disable (default) 1 ? internal power up/down sequence enable enref 2 0 ? disable reference 1 ? enable reference (default) vmidsel 1:0 00 ? vmid disabled 01 ? 50 k ? divider enabled 10 ? 500 k ? divide r enabled (default) 11 ? 5 k ? divider enabled 6.1.2 register 1 ? chip control 2, default 0001 1100 bit name bit description tsden 7 0 ? thermal shutdown disabled (default) 1 ? thermal shutdown enabled pdnoc 6 0 ? o ver c urrent shutdown disabled (default) 1 ? o ver c urrent shutdown enabled lpvcmmod 5 0 ? normal (default) 1 ? low power lpvrefbuf 4 0 ? normal 1 ? low power (default) p dnana 3 0 ? normal 1 ? entire analog power down (default) p dni biasgen 2 0 ? normal 1 ? ibiasgen power down (default) v reflo 1 0 ? normal (default) 1 ? low power p dnvrefbuf 0 0 ? normal (default) 1 ? power down 6.1.3 register 2 ? chip power management, default 1100 0011 bit name bit description adc_digpdn 7 0 ? normal
everest semiconductor ES8288 revision 6 .0 november 2016 12 1 ? resets adc dem, filter and serial data port (default) adc _stm_rst 5 0 ? normal (default) 1 ? reset adc state machine to power down state adc d ll_pdn 3 0 ? normal (default) 1 ? adc_dll power down , stop adc clock adcvref_pdn 1 0 ? adc analog reference power up 1 ? adc analog reference power down (default) 6.1.4 regi ster 3 ? adc power management, default 1111 1100 bit name bit description p dn ainl 7 0 ? normal 1 ? left analog input power down (default) p dn ainr 6 0 ? normal 1 ? right analog input power down (default) p dn adcl 5 0 ? left adc power up 1 ? left adc powe r down (default) p dn adcr 4 0 ? right adc power up 1 ? right adc power down (default) p dn micb 3 0 ? microphone bias power on 1 ? microphone bias power down (high impedance output, default) p dnadcbiasgen 2 0 ? normal 1 ? power down (default) flashlp 1 0 ? normal (default) 1 ? flash adc low power int1lp 0 0 ? normal (default) 1 ? int1 low power 6.1.5 register 5 ? chip low power 1 , default 0000 0000 bit name bit description oc[2] 4 0 ? over current setting (default) 1 ? over current setting oc[3] 2 0 ? ov er current setting (default) 1 ? over current setting 6.1.6 register 6 ? chip low power 2 , default 0000 0000 bit name bit description lppga 7 0 ? normal (default) 1 ? low power lpadcvrp 1 0 ? normal (default) 1 ? low power 6.1.7 register 7 ? a nalog voltage mana gement, default 0111 1100 bit name bit description
everest semiconductor ES8288 revision 6 .0 november 2016 13 vsel 6 :0 111110 0 ? normal (default) 6.1.8 register 8 ? master mode control , default 1000 0000 bit name bit description ms c 7 0 ? slave s erial port mode 1 ? master s erial port mode (default) mclkdiv2 6 0 ? mclk not divide (default) 1 ? mclk divide by 2 bclk_inv 5 0 ? normal (default) 1 ? bclk inverted bclkdiv 4: 0 0000 0 ? master mode bclk generated automatically based on the clock table (default) o thers ? mclk/n, n=1~31 6.2 adc control 6.2.1 register 9 ? adc contr ol 1, default 0000 0000 bit name bit description micampl 7:4 left channel pga gain 0000 ? 0 db ( default ) 0 001 ? + 3 db 0010 ? + 6 db 0011 ? + 9 db 0 100 ? + 12 db 0101 ? + 15 db 0110 ? + 18 db 0111 ? + 21 db 1000 ? + 24 db micampr 3:0 right channel pga gain 0000 ? 0db ( default ) 0 001 ? + 3 db 0010 ? + 6 db 0011 ? + 9 db 0 100 ? + 12 db 0101 ? + 15 db 0110 ? + 18 db 0111 ? + 21 db 1000 ? + 24 db 6.2.2 register 10 ? adc control 2, default 0000 0000 bit name bit description linsel 7:6 left channel input select 00 ? linput1 ( def ault ) 01 ? linput2 10 ? linput3
everest semiconductor ES8288 revision 6 .0 november 2016 14 11 ? l - r differential (either linput1 - rinput1 or linput2 - rinput2, selected by ds) rinsel 5:4 right channel input select 00 ? rinput1 ( default ) 01 ? rinput2 10 ? rinput3 11 ? l - r differential (either linput1 - rinput1 or linpu t2 - rinput2, selected by ds) 6.2.3 register 11 ? adc control 3 , default 0000 0110 bit name bit description ds 7 differential input select 0 ? linput1 - rinput1 (default) 1 ? linput2 - rinput2 monomix 4:3 00 ? stereo (default) 01 ? analog mono mix to left adc 10 ? analog mono mix to right adc 11 ? reserved tri 2 0 ? asdout is adc normal output (default) 1 ? asdout tri - stated , alrc k , dlrc k and sclk are inputs oc [1:0] 1:0 00 ? over current setting (default) 6.2.4 register 12 ? adc control 4 , default 0000 0000 bit name bit description datsel 7:6 00 ? left data = left adc, right data = right adc 01 ? left data = left adc, right data = left adc 10 ? left data = right adc, right data = right adc 11 ? left data = right adc, right data = left adc adclrp 5 i2s, left justif ied or right justified mode : 0 ? left and right normal polarity 1 ? left and right invert ed polarity dsp /pcm mode : 0 ? msb is available on 2nd bclk rising edge after a lrc k rising edge 1 ? msb is available on 1st bclk rising edge after a lrc k rising edge ad cwl 4:2 000 ? 24 - bit serial audio data word length 001 ? 20 - bit serial audio data word length 010 ? 18 - bit serial audio data word length 011 ? 16 - bit serial audio data word length 100 ? 32 - bit serial audio data word length adcformat 1:0 00 ? i2s serial au dio data format 01 ? left justify serial audio data format 10 ? right justify serial audio data format 11 ? dsp /pcm mode serial audio data format 6.2.5 register 13 ? adc control 5 , default 0000 0110 bit name bit description
everest semiconductor ES8288 revision 6 .0 november 2016 15 adc fsmode 5 0 ? single speed mode (default) 1 ? double speed mode adcfsratio 4 : 0 m aster mode adc mclk to sampling frequency ratio 00000 ? 128 00001 ? 192 00010 ? 256 00011 ? 384 00100 ? 512 00101 ? 576 00110 ? 768 (default) 00111 ? 1024 01000 ? 1152 01001 ? 1408 01010 ? 1536 01011 ? 21 12 01100 ? 2304 10000 ? 125 10001 ? 136 10010 ? 250 10011 ? 272 10100 ? 375 10101 ? 500 10110 ? 544 10111 ? 750 11000 ? 1000 11001 ? 1088 11010 ? 1496 11011 ? 1500 other ? reserved 6.2.6 register 14 ? adc control 6 , default 0011 0000 bit name bit descript ion adc_invl 7 0 ? normal (default) 1 ? left channel polarity inverted adc_invr 6 0 ? normal (default) 1 ? right channel polarity inverted a dc_ hpf _l 5 0 ? disable adc left channel high pass filter 1 ? enable adc left channel high pass filter (default) adc_ hpf _r 4 0 ? disable adc right channel high pass filter 1 ? enable adc right channel high pass filter (default) 6.2.7 register 15 ? adc control 7 , default 0011 0000 bit name bit description adcramprate 7:6 00 ? 0.5 db per 4 lrck digital volume control r amp rate (default) 01 ? 0.5 db per 8 lrck digital volume control ramp rate 10 ? 0.5 db per 16 lrck digital volume control ramp rate 11 ? 0.5 db per 32 lrck digital volume control ramp rate adcsoftramp 5 0 ? disabled digital volume control soft ramp 1 ? en abled digital volume control soft ramp (default) adczerocrs 4 0 ? disabled digital volume control change at zero cross 1 ? enabled digital volume control change at zero cross (default) adcler 3 0 ? normal (default) 1 ? both channel gain control is set by adc left gain control register adcmute 2 0 ? normal (default) 1 ? mute adc digital output
everest semiconductor ES8288 revision 6 .0 november 2016 16 6.2.8 register 16 ? adc control 8 , default 1100 0000 bit name bit description ladcvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to ? 96 db. 00000000 ? 0 db 00000001 ? - 0.5 db 00000010 ? - 1 db ? 11000000 ? - 96 db (default) 6.2.9 register 17 ? adc control 9 , default 1100 0000 bit name bit description radcvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to ? 96 db. 00000000 ? 0 db 00000001 ? - 0.5 db 00000010 ? - 1 db ? 11000000 ? - 96 db (default) 6.2.10 register 18 ? adc control 10 , default 0011 1000 bit name bit description alcsel 7:6 00 ? alc off 01 ? alc right channel only 10 ? alc left channel only 11 ? alc s tereo maxgain 5:3 set maximum gain of pga 000 ? - 6.5 db 001 ? - 0.5 db 010 ? 5.5 db 011 ? 11.5 db 100 ? 17.5 db 101 ? 23.5 db 110 ? 29.5 db 111 ? 35.5 db mingain 2 :0 set minimum gain of pga 000 ? - 12 db 001 ? - 6 db 010 ? 0 db 011 ? +6 db 100 ? +12 db 101 ? +18 db 110 ? +24 db 111 ? +30 db
everest semiconductor ES8288 revision 6 .0 november 2016 17 6.2.11 register 19 ? adc control 11 , default 1011 0000 bit name bit description alcl vl 7:4 alc target 0000 ? ? 2 2 .5dbfs 0001 ? ? 2 1 .0dbfs ?? 11 00 ? ? 4.5 dbfs 11 01 ? ? 3 dbfs 1110 ? ? 1.5 dbfs 1111 ? ? 1.5 dbfs alc hld 3:0 alc hold ti me before gain is increased 0000 ? 0ms 0001 ? 2.67ms 0010 ? 5.33ms ?? (time doubles with every step) 1001 ? 0.68s 1 010 or higher ? 1.36 s 6.2.12 register 20 ? adc control 1 2 , default 0011 0010 bit name bit description alc dcy 7:4 alc decay (gain ramp up) time, a lc mode / limiter mode: 0000 ? 410 us / 90.8 us 0001 ? 820 us / 182us 0010 ? 1.64 ms / 363us ?? (time doubles with every step) 1001 ? 210 ms/46.5 ms 1010 or higher ? 420 ms/93 ms alc atk 3:0 alc attack (gain ramp down) time, a lc mode / limiter mode: 0000 ? 104 us/ 2 2.7 us 0001 ? 208 us/ 45.4 u s 0010 ? 416 us/ 90.8 u s ?? (time doubles with very step) 1001 ? 53.2 ms/ 11.6 ms 1010 or higher ? 106 ms/ 23.2 ms
everest semiconductor ES8288 revision 6 .0 november 2016 18 6.2.13 register 21 ? adc control 1 3 , default 0000 0110 6.2.14 register 22 ? adc control 1 4 , default 0000 0000 bit name bit description ngth 7:3 noise gate threshold 00000 ? - 76.5 dbfs 00001 ? - 75 dbfs ?? 11110 ? - 31.5 dbfs 11111 ? - 30 dbfs ngg 2:1 noise gate type x0 ? pga gain held constant 01 ? mute adc output 11 ? reserved ngat 0 noise gate function enable 0 ? disable 1 ? enable 6.2.15 register 43 ? adc control 15, default 0011 1000 bit name bit description slrck 7 0 ? daclrc and adclrc separate (default) 1 ? daclrc and adclrc same lrck_sel 6 master mode , if slrck = 1 then 0 ? use dac lrck (default) 1 ? use adc lrck adc_dll_pwd 3 0 ? normal (default) 1 ? adc dll power down bit name bit description alcmode 7 determines the alc mode of ope ration: 0 ? alc mode (normal operation) 1 ? limiter mode. alczc 6 alc uses zero cross detection circuit. 0 ? d isable (recommended) 1 ? e nable time_out 5 zero cross time out 0 ? disable (default) 1 ? enable win_size 4:0 windows s ize for peak detector set the window size to n*16 samples 00110 ? 96 samples (default) 00111 ? 102 samples ? .. 11111 ? 496 samples
everest semiconductor ES8288 revision 6 .0 november 2016 19 7 d igital audio interface the device provides four formats of serial audio data interface for the output from the adc through lrck, sclk and sdout pins. the four formats are i 2 s, left justified, right justified and dsp/pcm mode. adc data is out on asdout and change s on the falling edge of asclk. the relationship of sdata (sdout) , sclk and lrck with the three formats is shown through figure 3 to figure 7. n-2 n-1 n 3 2 1 1 sclk msb lsb left channel n-2 n-1 n 3 2 1 1 sclk msb lsb right channel sdata sclk lrck figure 3 i 2 s serial audio data format up to 24 - bit n-2 n-1 n 3 2 1 msb lsb left channel n-2 n-1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 4 left justified serial audio data format up to 24 - bit n-2 n-1 n 3 2 1 msb lsb left channel n-2 n-1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 5 right justified serial audio data format up to 24 - bit figure 6 dsp /pcm mode a
everest semiconductor ES8288 revision 6 .0 november 2016 20 figure 7 dsp /pcm mode b 8 electrical character istics 8.1 absolute maximum ra tings continuous operation at or beyond these condition s may permanent ly damage the device. parameter min max analog supply voltage level - 0.3v +5.0v digital supply voltage level - 0.3v +5.0v input voltage range dgnd - 0.3v dvdd+0.3v operating temperature range - 40 c +85 c storage temperature - 65 c +150 c 8.2 recommended operating conditions parameter min typ max unit analog supply voltage level 1.7 3.3 3.6 v digital supply voltage level 1.5 1.8 3.6 v 8.3 adc analog and filter characteristics and specificatio ns test condition s are as the following unless otherwise specify: avdd=+ 3 . 3 v, dvdd=+ 1 . 8 v, agnd=0v, dgnd=0v, ambient temperature=+25 c , fs=48 khz , 96 khz or 192 khz , mclk/lrck=256. parameter min typ max unit a d c performance dynamic range (note 1) 85 95 98 db thd + n - 88 - 85 - 75 db channel separation (1khz) 80 85 90 db sign al to noise ratio 85 95 98 db interchannel gain mismatch 0.1 db gain error 5 % filter frequency response ? single speed passband 0 0.45 35 fs
everest semiconductor ES8288 revision 6 .0 november 2016 21 stopband 0.54 65 fs passband r ipple 0.05 db stopband attenuation 50 db filter frequency response ? double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 50 db analog input full scale input level avdd/3.3 vrms input impedance 20 k note 1. the value is measured used a - weighted filter. 8.4 power consumption characteristics parameter min typ max unit normal operation mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v: record dvdd=3.3v, pvdd=3.3v, avdd=3.3v: record 9 30 m w powe r down mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v dvdd=3.3v, pvdd=3.3v, avdd=3.3v 0.3 1.9 m w 8.5 serial audio port switching specifications parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz lrck duty cy cle 40 60 % sclk frequency 26 mhz sclk pulse width low t sclkl 15 ns sclk pulse width high t sclkh 15 ns sclk falling to lrck edge t slr C10 10 ns sclk falling to sdout valid t sdo 0 ns sdin valid to sclk rising setup time t sdis 10 ns sclk rising to sdin hold time t sdih 10 ns
everest semiconductor ES8288 revision 6 .0 november 2016 22 8.6 serial control port switching specifications parameter symbol min max unit spi mode spi_clk clock frequency 10 mhz spi_clk edge to spi_csn falling t spics 5 ns spi_csn high time between transmissions t spish 500 n s spi_csn falling to spi_clk edge t spisc 10 ns spi_clk low time t spicl 45 ns spi_clk high time t spich 45 ns spi_din to spi_clk rising setup time t spids 10 ns spi_clk rising to data hold time t spidh 15 ns 2 - wire mode scl clock frequency f scl 1 00 khz bus free time between transmissions t twid 4.7 us start condition hold time t twsth 4.0 us clock low time t twcl 4.0 us clock high time t twch 4.0 us setup time for repeated start condition t twsts 4.7 us sda hold time from scl falling t tw dh 0.1 us sda setup time to scl rising t twds 100 ns rise time of scl t twr 25 us fall time scl t twf 25 ns figure 8 serial audio port timing
everest semiconductor ES8288 revision 6 .0 november 2016 23 spi_din spi_clk spi_csn t spics t spisc t spids t spidh t spich t spicl t spish s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid figure 10 serial control port 2 - wire timing figure 9 serial control port spi timing
everest semiconductor ES8288 revision 6 .0 november 2016 24 9 package information
everest semiconductor ES8288 revision 6 .0 november 2016 25 10 corpoaration information everest semiconductor co., ltd. ??? 328 ?????? 6a ? 215028 email: info@everest - semi.com

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